This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-353172, filed Dec. 13, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor memory device and more particularly to a fast cycle synchronous DRAM (SDR-FCRAM) having a function of rapidly reading/writing random data from or into a memory cell array and a data write system of a double data rate synchronous DRAM (DDR-FCRAM) for realizing the data transfer rate twice that of the above DRAM.
In order to enhance the data access speed of the DRAM to that of an SDRAM and attain a large data band width (the number of data bytes for each unit time) by use of a high clock frequency (tCK), a synchronous DRAM (SDRAM) is invented and is already put into practice from the 4-Mbit or 16-Mbit DRAM generation. In the present 64-Mbit generation, the SDARM occupies a large part of the amount of all of the DRAMs used.
Recently, in order to further enhance the operation speed of the SDRAM, a double data rate SDRAM which is operated at the data transfer rate twice that of the conventional case by operating the same in synchronism with both of the leading edge and trailing edge of a clock signal is proposed and actively commercialized.
In order to enhance the data transfer rate in the SDRAM, the data bandwidth is actively increased, but it is difficult to make random access to cell data in a memory core, that is, to enhance the speed of data access to a row address which has been changed to indicate a different row. This is because the cycle time (random cycle time=tRC) of the memory core cannot be greatly reduced since a certain period of time (which is referred to as core latency) is required for the destructive readout and amplifying operation inherent to the DRAM and the precharge operation prior to the next access to the memory core in the SDRAM.
In order to solve the above problem, a so-called fast cycle RAM (FCRAM) in which access to the memory core and the precharge operation thereof are pipelined to reduce the random cycle time of the conventional DRAM to half or less is proposed and will be started to be commercialized mainly in the network field in which random data of a router or LAN switch using SRAMs in the prior art is transferred at high speed.
The basic system of the data readout operation of the FCRAM is described in International Application (International Publication Number WO98/56004 (Fujioka et al.) using Jpn. Pat. Appln. Nos. 09-145406, 09-215047 and 09-332739 as the basic application, for example.
This invention is to improve the data write operation of the FCRAM defined in the above International Application.
Accordingly, an object of this invention is to provide a semiconductor memory device capable of reducing random cycle time at the write time by reducing the data path when data is written into a memory cell based on the contents of an address register.
Further, another object of this invention is to provide a semiconductor memory device capable having a reduced chip size by reducing the pattern occupying area of a data register.
In addition, still another object of this invention is to provide a fast cycle random access memory having an improved data write operation.
Another object of this invention is to provide an improved data write method for a fast cycle random access memory.
The above object of this invention can be attained by a semiconductor memory device comprising a memory core section; an address register provided in the memory core section, for latching an address of a memory cell which is a to-be-written object; a data register provided in the memory core section, for latching data to be written into the memory cell; and DQ write drivers arranged in the memory core section in a repeated pattern at a pitch which is substantially a multiple of that of bit line pairs, each for driving a corresponding data line pair according to write data latched in the data register; wherein timing the writing of data fetched from the exterior in response to a command is started when a next command is set.
Also, the above object of this invention can be attained by a semiconductor memory device comprising a memory core section; an address register provided in the memory core section, for latching an address of a memory cell which is a to-be-written object; a data register provided in the memory core section, for latching data to be written into the memory cell; a DQ write driver arranged in the memory core section, for driving a corresponding data line pair according to write data latched in the data register; a DQ read amplifier provided in correspondence to the DQ write driver in the memory core section, for amplifying readout data read out on the data line pair; a coherency detector for determining whether or not an input address coincides with an address which is stored in the address register and in which the data write operation into the memory cell is not yet actually completed; and a switching circuit for selectively supplying one of the readout data amplified by the DQ read amplifier and data latched in the data register to a readout data line in response to an output signal of the coherency detector; wherein the operation for writing data latched in the data register into the memory cell by input of a write command is started in response to input of a write command in a next clock cycle, the sense operation of data on the data line pair is interrupted when a read command is input before the next write command at the write time and coincidence of the addresses is detected in the coherency detector and data latched in the data register is selected instead of the amplification result of the DQ read amplifier by use of the switching circuit, transferred to the readout data line pair and output to the exterior.
Further, the above object of this invention can be attained by a fast cycle random access memory comprising a clock buffer supplied with a clock signal used as a reference of operation timing from the exterior; a command decoder and controller supplied with a control signal and command, for decoding the command and controlling the operations of circuits based on the result of decoding and the control signal; an address buffer supplied with an address signal, for outputting a row address signal and column address signal in response to the clock signal supplied from the clock buffer; an address register connected to the address buffer, for holding address information of a memory cell subjected to a late write operation; a memory cell array having memory cells arranged therein; a row decoder for decoding a row address signal supplied from the address buffer to select the row of a memory cell in the memory cell array; a column decoder for decoding a column address signal supplied from the address buffer to specify the column of a memory cell in the memory cell array; a sense amplifier and I/O gate for sensing and amplifying data to be written into the memory cell or data read out from the memory cell and then transferring the data; an I/O control circuit for controlling input/output of data; a data input buffer to which write data input to a data pin is input, the write data input to the data input buffer being supplied to a selected one of the memory cells in the memory cell array via the I/O control circuit and the sense amplifier and I/O gate; an input data register connected to the data input buffer, for holding write data information of a memory cell subjected to the late write operation; a data output buffer to which readout data from a selected one of the memory cells in the memory cell array is supplied via the sense amplifier and I/O gate and the I/O control circuit, the data output buffer outputting readout data from the data pin; and a control signal generator supplied with an output signal of the clock buffer and an output signal of the command decoder and controller, for generating control signals for controlling the row decoder, column decoder, input data register, I/O control circuit, data input buffer and data output buffer; wherein the memory cell array, address register, row decoder, column decoder, sense amplifier and I/O gate and I/O control circuit are arranged in a memory core section and the clock buffer, command decoder and controller, address buffer, control signal generator, data input buffer and data output buffer are arranged in a peripheral area of the memory core section.
Further, the above object of this invention can be attained by a data write method for a fast cycle random access memory comprising the steps of supplying serial data input to a data pin from the exterior to a data input buffer, converting the serial data into parallel data in a serial/parallel converting circuit and then transferring the parallel data to an input data register provided adjacent to a DQ write driver via a write data line; and writing data latched in the input data register in a preceding write cycle into a memory cell via the DQ write driver, data line pair, I/O gate and bit line pair when data is written into the memory cell in a next write cycle.
Also, the above object of this invention can be attained by a data write method for a fast cycle random access memory comprising the steps of supplying a write command used as a first command and a column address latch command used as a second command as one packet; fetching the write command and column address latch command in synchronism with two successive clock signals; generating a write gate pulse in response to input of the write command to activate a DQ write driver and drive the data line pair according to the contents of an internal node of an input data register; and selecting a column selection line in response to input of the column address latch command, turning ON an I/O gate to transfer data on the data line pair to a bit line pair and writing the data into a memory cell.
With the above construction, since the data register is arranged in a position near the memory cell in the memory core section, it becomes possible to transfer data to the upstream side of a data path of write data to the memory cell, enhance the speed of the operation for writing data into the memory cell and reduce the random cycle time at the write time in a next write cycle.
Further, the latch circuit used as the data register can be formed with an extremely simple construction and constructed by transistors having a small driving ability. Therefore, the data register can be easily buried in a repeatedly arranged portion of the conventional DQ read amplifier and DQ write driver and interconnections for signals in internal nodes of the data register can be extremely easily formed. As a result, an increase in the chip size can be suppressed.
Further, in the late write operation, if a read command is supplied before a next write command and the command coincides with an address which is stored in the address register and in which the data write operation into the memory cell is not yet actually completed, data from the data register can be directly read out instead of data from the memory cell.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.